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| Date Nov. 29. 2001 8M (x8/x16) Flash Memory LH28F800BJE-PBTL70 LHF80J47 qHandle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. qWhen using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics *Instrumentation and measuring equipment *Machine tools *Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers *Traffic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *Aerospace equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry *Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. qPlease direct all queries regarding the products covered herein to a sales representative of the company. Rev. 1.27 LHF80J47 1 CONTENTS PAGE 1 INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. 8 3.2 Output Disable.............................................................. 8 3.3 Standby......................................................................... 8 3.4 Reset............................................................................. 8 3.5 Read Identifier Codes................................................... 9 3.6 OTP(One Time Program) Block .................................. 9 3.7 Write........................................................................... 10 4 COMMAND DEFINITIONS........................................... 10 4.1 Read Array Command................................................ 12 4.2 Read Identifier Codes Command ............................... 12 4.3 Read Status Register Command ................................. 12 4.4 Clear Status Register Command................................. 12 4.5 Block Erase Command............................................... 13 4.6 Full Chip Erase Command ......................................... 13 4.7 Word/Byte Write Command....................................... 13 4.8 Block Erase Suspend Command ................................ 14 4.9 Word/Byte Write Suspend Command ........................ 14 4.10 Set Block and Permanent Lock-Bit Commands ....... 15 4.11 Clear Block Lock-Bits Command ............................ 15 4.12 OTP Program Command .......................................... 16 4.13 Block Locking by the WP# ...................................... 16 PAGE 5 DESIGN CONSIDERATIONS ....................................... 27 5.1 Three-Line Output Control ........................................ 27 5.2 RY/BY# and WSM Polling ....................................... 27 5.3 Power Supply Decoupling ......................................... 27 5.4 VCCW Trace on Printed Circuit Boards ..................... 27 5.5 VCC, VCCW, RP# Transitions .................................... 27 5.6 Power-Up/Down Protection....................................... 28 5.7 Power Dissipation ...................................................... 28 5.8 Data Protection Method ............................................. 28 6 ELECTRICAL SPECIFICATIONS ................................ 29 6.1 Absolute Maximum Ratings ...................................... 29 6.2 Operating Conditions ................................................. 29 6.2.1 Capacitance .......................................................... 29 6.2.2 AC Input/Output Test Conditions ........................ 30 6.2.3 DC Characteristics ............................................... 31 6.2.4 AC Characteristics - Read-Only Operations ........ 33 6.2.5 AC Characteristics - Write Operations ................ 36 6.2.6 Alternative CE#-Controlled Writes...................... 38 6.2.7 Reset Operations .................................................. 40 6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance ................. 41 Rev. 1.27 LHF80J47 2 LH28F800BJE-PBTL70 8M-BIT ( 512Kbit x16 / 1Mbit x8 ) Boot Block Flash MEMORY s Low Voltage Operation VCC=VCCW=2.97V-3.63V Single Voltage s Enhanced Automated Suspend Options Word/Byte Write Suspend to Read Block Erase Suspend to Word/Byte Write Block Erase Suspend to Read s OTP(One Time Program) Block 3963 word + 4 word Program only array s User-Configurable x8 or x16 Operation s High-Performance Read Access Time 70ns(VCC=2.97V-3.63V) s Enhanced Data Protection Features s Operating Temperature 0C to +70C Absolute Protection with VCCWVCCWLK Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Lockout during Power Transitions Block Locking with Command and WP# Permanent Locking s Low Power Management Typ. 2A (VCC=3.0V) Standby Current Automatic Power Savings Mode Decreases ICCR in Static Mode Typ. 120A (VCC=3.0V, TA=+25C, f=32kHz) Read Current s Automated Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Command User Interface (CUI) Status Register (SR) s SRAM-Compatible Write Interface s Industry-Standard Packaging 48-Lead TSOP s Optimized Array Blocking Architecture Two 4K-word (8K-byte) Boot Blocks Six 4K-word (8K-byte) Parameter Blocks Fifteen 32K-word (64K-byte) Main Blocks Bottom Boot Location s ETOXTM* Nonvolatile Flash Technology s CMOS Process (P-type silicon substrate) s Not designed or rated as radiation hardened s Extended Cycling Capability Minimum 100,000 Block Erase Cycles The product is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The product can operate at VCC=2.97V-3.63V and VCCW=2.97V-3.63V or 11.7V-12.3V. Its low voltage operation capability realize battery life and suits for cellular phone application. Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the product offers four levels of protection: absolute protection with VCCWVCCWLK, selective hardware block locking or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The product is manufactured on SHARP's 0.25m ETOXTM* process technology. It come in industry-standard package: the 48-lead TSOP, ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. Rev. 1.27 LHF80J47 3 1 INTRODUCTION This datasheet contains the product specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of the product are: *Single low voltage operation *Low power consumption *Enhanced Suspend Capabilities *Boot Block Architecture Please note following: *VCCWLK has been lowered to 1.0V to support 2.97V3.63V block erase, full chip erase, word/byte write and lock-bit configuration operations. The VCCW voltage transitions to GND is recommended for designs that switch VCCW off during read operation. A block erase operation erases one of the device's 32Kword/64K-byte blocks typically within 1.2s (3V VCC, 3V VCCW), 4K-word/8K-byte blocks typically within 0.6s (3V VCC, 3V VCCW) independent of other blocks. Each block can be independently erased minimum 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in word/byte increments of the device's 32K-word blocks typically within 33s (3V VCC, 3V VCCW), 64K-byte blocks typically within 31s (3V VCC, 3V VCCW), 4K-word blocks typically within 36s (3V VCC, 3V VCCW), 8Kbyte blocks typically within 32s (3V VCC, 3V VCCW). Word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. Individual block locking uses a combination of bits, thirtynine block lock-bits, a permanent lock-bit and WP# pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word/byte write operations, while the permanent lock-bit gates block lock-bit modification and locked block alternation. Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSM's block erase, full chip erase, word/byte write or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, full chip erase, word/byte write or lock-bit configuration. RY/BY#-high Z indicates that the WSM is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in reset mode. 1.2 Product Overview The product is a high-performance 8M-bit Boot Block Flash memory organized as 512K-word of 16 bits or 1Mbyte of 8 bits. The 512K-word/1M-byte of data is arranged in two 4K-word/8K-byte boot blocks, six 4K-word/8Kbyte parameter blocks and fifteen 32K-word/64K-byte main blocks which are individually erasable, lockable and unlockable in-system. The memory map is shown in Figure 3. The dedicated VCCW pin gives complete data protection when VCCWVCCWLK. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, full chip erase, word/byte write and lock-bit configuration operations. Rev. 1.27 LHF80J47 The access time is 70ns (tAVQV) over the operating temperature range (0C to +70C) and VCC supply voltage range of 2.97V-3.63V. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 2A (CMOS) at 3.0V VCC. When CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. When the RP# pin is at GND, reset mode is enabled which minimizes power consumption and provides write protection. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. Please do not execute reprogramming "0" for the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprogramming "0" to the data which has been programed "1". *Program "0" for the bit in which you want to change data from "1" to "0". *Program "1" for the bit which has already been programmed "0". For example, changing data from "10111101" to "10111100" requires "11111110" programming. 4 1.3 Product Description 1.3.1 Package Pinout The product is available in 48-lead TSOP package (see Figure 2). 1.3.2 Block Organization This product features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times. For the address locations of the blocks, see the memory map in Figure 3. Boot Blocks: The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller-based system. This boot block 4K words (4,096words) features hardware controllable writeprotection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the VCCW, RP#, WP# pins and block lock-bit. Parameter Blocks: The boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each boot block component contains six parameter blocks of 4K words (4,096 words) each. The protection of the parameter block is controlled using a combination of the VCCW, RP# and block lock-bit. Main Blocks: The reminder is divided into main blocks for data or code storage. Each 8M-bit device contains fifteen 32K words (32,768 words) blocks. The protection of the main block is controlled using a combination of the VCCW, RP# and block lock-bit. Rev. 1.27 LHF80J47 5 DQ0-DQ15 Output Buffer Input Buffer Output Multiplexer Identifier Register Data Register Status Register Command User Interface I/O Logic VCC BYTE# CE# WE# OE# RP# WP# Data Comparator A-1-A18 Input Buffer Y Decoder Y-Gating Write State Machine Main Block 13 Main Block 14 OTP Block RY/BY# Program/Erase Voltage Switch VCCW Main Block 0 Main Block 1 Boot Block 0 Boot Block 1 Parameter Block 0 Parameter Block 1 Parameter Block 2 Parameter Block 3 Parameter Block 4 Parameter Block 5 Address Latch X Decoder 32K-Word (64K-Byte) Main Blocks x15 VCC GND Address Counter Figure 1. Block Diagram A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RP# VCCW WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-LEAD TSOP STANDARD PINOUT 12mm x 20mm TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 Figure 2. TSOP 48-Lead Pinout Rev. 1.27 LHF80J47 6 Symbol A-1 A0-A18 Type INPUT DQ0-DQ15 INPUT/ OUTPUT CE# RP# OE# WE# WP# INPUT INPUT INPUT INPUT INPUT BYTE# INPUT OPEN DRAIN OUTPUT RY/BY# VCCW SUPPLY Table 1. Pin Descriptions Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. A-1: Lower address input while BYTE# is VIL. A-1 pin changes DQ15 pin while BYTE# is VIH. A15-A18: Main Block Address. A12-A18: Boot and Parameter Block Address. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ8-DQ15 pins are not used while byte mode (BYTE#=VIL). Then, DQ15 pin changes A-1 address input. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET: Resets the device internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from reset mode sets the device to read array mode. RP# must be VIL during power-up. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. WRITE PROTECT: When WP# is VIL, boot blocks cannot be written or erased. When WP# is VIH, locked boot blocks can not be written or erased. WP# is not affected parameter and main blocks. BYTE ENABLE: BYTE# VIL places device in byte mode (x8). All data is then input or output on DQ0-7, and DQ8-15 float. BYTE# VIH places the device in word mode (x16), and turns off the A-1 input buffer. READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, full chip erase, word/byte write or lock-bit configuration). RY/BY#-high Z indicates that the WSM is ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode. BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words/bytes or configuring lock-bits. With VCCWVCCWLK, memory contents cannot be altered. Block erase, full chip erase, word/byte write and lock-bit configuration with an invalid VCCW (see 6.2.3 DC Characteristics) produce spurious results and should not be attempted. Applying 12V0.3V to VCCW during erase/write can only be done for a maximum of 1000 cycles on each block. VCCW may be connected to 12V0.3V for a total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see 6.2.3 DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated. VCC GND NC SUPPLY SUPPLY Rev. 1.27 LHF80J47 7 2 PRINCIPLES OF OPERATION The product includes an on-chip WSM to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. It allows for: fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset mode (see section 3 Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VCCW voltage. High voltage on VCCW enables successful block erase, full chip erase, word/byte write and lock-bit configurations. All functions associated with altering memory contents-block erase, full chip erase, word/byte write, lock-bit configuration, status and identifier codes-are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, full chip erase, word/byte write and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. Interface software that initiates and polls progress of block erase, full chip erase, word/byte write and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. [A18-A0] 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000 Bottom Boot 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 32KW/64KB Main Block 4KW/8KB Parameter Block 4KW/8KB Parameter Block 4KW/8KB Parameter Block 4KW/8KB Parameter Block 4KW/8KB Parameter Block 4KW/8KB Parameter Block 4KW/8KB Boot Block 4KW/8KB Boot Block 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 1 0 [A18-A-1] 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 00E000 00DFFF 00C000 00BFFF 00A000 009FFF 008000 007FFF 006000 005FFF 004000 003FFF 002000 001FFF 000000 Figure 3. Memory Map Rev. 1.27 LHF80J47 8 2.1 Data Protection When VCCWVCCWLK, memory contents cannot be altered. The CUI, with two-step block erase, full chip erase, word/byte write or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VCCW. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and word/byte write operations. Refer to Table 5 for write protection alternatives. 3.3 Standby CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a highimpedance state independent of OE#. If deselected during block erase, full chip erase, word/byte write or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 Reset RP# at VIL initiates the reset mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100ns. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, full chip erase, word/byte write or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full chip erase, word/byte write or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP's flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the VCCW voltage. RP# can be at VIH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. Six control pins dictate the data flow in and out of the component: CE#, OE#, BYTE#, WE#, RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0-DQ15) control and when active drives the selected memory data onto the I/O bus. BYTE# is the device I/O interface mode control. WE# must be at VIH, RP# must be at VIH, and BYTE# and WP# must be at VIL or VIH. Figure 16, 17 illustrates read cycle. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ15) are placed in a high-impedance state. Rev. 1.27 LHF80J47 9 3.5 Read Identifier Codes The read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting. Bottom Boot Reserved for Future Implementation 78003 78002 78001 78000 77FFF 10000 0FFFF 3.6 OTP(One Time Program) Block The OTP block is a special block that can not be erased. The block is divided into two parts. One is a factory program area where a unique number can be written according to customer requirements in SHARP factory. This factory program area is "READ ONLY" (Already locked). The other is a customer program area that can be used by customers. This customer program area can be locked. After locking, this customer program area is protected permanently. The OTP block is read in Configuration Read Mode by writing Read Identifier Codes command(90H). To return to Read Array Mode, write Read Array command(FFH). The OTP block is programmed by writing OTP Program command(C0H). First write OTP Program command and then write data with address to the device (See Figure 5). If OTP program is failed, SR.4(WORD/BYTE WRITE AND SET LOCK-BIT STATUS) bit is set to "1". And if this OTP block is locked, SR.1(DEVICE PROTECT STATUS) bit is set to "1" too. The OTP block is also locked by writing OTP Program command(C0H). First write OTP Program command and then write data "FFFDH" with address "80H" to the device. Address "80H" of OTP block is OTP lock information. Bit 0 of address "80H" means factory program area lock status("1" is "NOT LOCKED", "0" is "LOCKED"). Bit 1 of address "80H" means customer program area lock status. The OTP lock information can not be cleared, after once it is set. [A18-A0] 7FFFF [A18-A-1] FFFFF F0006 F0005 F0004 F0003 Main Block 14 Lock Configuration Code Reserved for Future Implementation Main Block 14 F0000 (Main Blocks 1 through 13) Reserved for Future Implementation 20000 EFFFF 1FFFF 01006 10005 10004 10003 08003 08002 08001 08000 07FFF Main Block 0 Lock Configuration Code Reserved for Future Implementation Main Block 0 10000 Reserved for Future Implementation 0FFFF 0E006 0E005 0E004 0E003 07003 07002 07001 07000 06FFF 03000 02FFF Parameter Block 5 Lock Configuration Code Reserved for Future Implementation Parameter Block 5 0E000 (Parameter Blocks 1 through 4) Reserved for Future Implementation 0DFFF 06000 05FFF 04006 04005 04004 04003 [A18-A0] 00FFF [A18-A-1] 01FFF 02003 02002 02001 02000 01FFF Parameter Block 0 Lock Configuration Code Reserved for Future Implementation Parameter Block 0 04000 03FFF Customer Program Area Reserved for Future Implementation 01003 01002 01001 01000 00FFF 00080 0007F 00004 00003 00002 00001 00000 Boot Block 1 Lock Configuration Code Reserved for Future Implementation Boot Block 1 02000 01FFF 02006 02005 02004 02003 00085 00084 00081 00080 0010A Factory Program Area OTP Lock 00109 00102 00100 OTP Block Reserved for Future Implementation Permanent Lock Configuration Code Boot Block 0 Lock Configuration Code Device Code Manufacturer Code Boot Block 0 00100 000FF 00008 00007 00006 00005 00004 00003 00002 00001 00000 Customer Program Area Lock(Bit 1) Factory Program Area Lock(Bit 0) Figure 5. OTP Block Address Map Figure 4. Device Identifier Code Memory Map Rev. 1.27 LHF80J47 10 3.7 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCC=2.97V-3.63V and VCCW=VCCWH1/2, the CUI additionally controls block erase, full chip erase, word/byte write and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Full Chip Erase command requires appropriate command data and an address within the device. The Word/Byte Write command requires the command and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 18 and 19 illustrate WE# and CE# controlled write operations. 4 COMMAND DEFINITIONS When the VCCW voltage VCCWLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VCCWH1/2 on VCCW enables successful block erase, full chip erase, word/byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands. Mode Read Output Disable Standby Reset Read Identifier Codes Write Notes 8 4 8 6,7,8 Table 2.1. RP# VIH VIH VIH VIL VIH VIH Table 2.2. RP# VIH VIH VIH VIL VIH Bus Operations (BYTE#=VIH)(1,2) CE# OE# WE# Address VIL VIL VIH X VIL VIH VIH X VIH X X X X X X X See VIL VIL VIH Figure 4, 5 VIL VIH VIL X Bus Operations (BYTE#=VIL)(1,2) CE# OE# WE# Address VIL VIL VIH X VIL VIH VIH X VIH X X X X X X X See VIL VIL VIH Figure 4, 5 VIL VIH VIL X VCCW X X X X X X DQ0-15 DOUT High Z High Z High Z Note 5 DIN RY/BY#(3) X X X High Z High Z X Mode Read Output Disable Standby Reset Read Identifier Codes Notes 8 4 8 VCCW X X X X X DQ0-7 DOUT High Z High Z High Z Note 5 RY/BY#(3) X X X High Z High Z Write 6,7,8 VIH X DIN X NOTES: 1. Refer to DC Characteristics. When VCCWVCCWLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control pins and addresses, and VCCWLK or VCCWH1/2 for VCCW. See DC Characteristics for VCCWLK voltages. 3. RY/BY# is VOL when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or reset mode. 4. RP# at GND0.2V ensures the lowest power consumption. 5. See Section 4.2 for read identifier code data. 6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed when VCCW=VCCWH1/2 and VCC=2.97V-3.63V. 7. Refer to Table 3 for valid DIN during a write operation. 8. Never hold OE# low and WE# low at the same timing. Rev. 1.27 LHF80J47 Table 3. Command Definitions(10) Bus Cycles First Bus Cycle (1) Req'd. Notes Oper Addr(2) Data(3) 1 Write X FFH 4 Write X 90H 2 2 Write X 70H 1 Write X 50H 2 5 Write X 20H 2 Write X 30H 40H or 2 5,6 Write X 10H 11 Command Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Full Chip Erase Word/Byte Write Oper(1) Read Read Write Write Write Second Bus Cycle Addr(2) Data(3) IA X BA X WA ID SRD D0H D0H WD Block Erase and Word/Byte 1 5 Write X B0H Write Suspend Block Erase and Word/Byte 1 5 Write X D0H Write Resume Set Block Lock-Bit 2 8 Write X 60H Write BA 01H Clear Block Lock-Bits 2 7,8 Write X 60H Write X D0H Set Permanent Lock-Bit 2 9 Write X 60H Write X F1H OTP Program 2 Write X C0H Write OA OD NOTES: 1. BUS operations are defined in Table 2.1 and Table 2.2. 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. BA=Address within the block being erased or locked. WA=Address of memory location to be written. OA=Address of OTP block to be written: see Figure 5. 3. ID=Data read from identifier codes. SRD=Data read from status register. See Table 6 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). OD=Data to be written at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). 4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and permanent lock configuration codes. See Section 4.2 for read identifier code data. 5. If WP# is VIL, boot blocks are locked without block lock-bits state. If WP# is VIH, boot blocks are locked by block lockbits. The parameter and main blocks are locked by block lock-bits without WP# state. 6. Either 40H or 10H are recognized by the WSM as the word/byte write setup. 7. The clear block lock-bits operation simultaneously clears all block lock-bits. 8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done. 9. Once the permanent lock-bit is set, permanent lock-bit reset is unable. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 1.27 LHF80J47 12 4.1 Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, full chip erase, word/byte write or lock-bit configuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word/Byte Write Suspend command. The Read Array command functions independently of the VCCW voltage and RP# can be VIH. 4.3 Read Status Register Command The status register may be read to determine when a block erase, full chip erase, word/byte write or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VCCW voltage. RP# can be VIH. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer, device, block lock configuration and permanent lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VCCW voltage and RP# can be VIH. Following the Read Identifier Codes command, the following information can be read: Table 4. Identifier Codes Address(2) Data(3) Code [A18-A0] [DQ7-DQ0] Manufacture Code 00000H B0H Device Code 00001H EDH Block Lock Configuration BA(1)+2 DQ0=0 *Block is Unlocked *Block is Locked *Reserved for Future Use Permanent Lock Configuration *Device is Unlocked *Device is Locked 00003H DQ0=0 DQ0=1 DQ0=1 DQ1-7 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VCCW Voltage. RP# can be VIH. This command is not functional during block erase or word/byte write suspend modes. DQ1-7 *Reserved for Future Use NOTE: 1. BA selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. 2. A-1 don't care in byte mode. 3. DQ15-DQ8 outputs 00H in word mode. Rev. 1.27 LHF80J47 13 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH/FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 6). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VCC=2.97V-3.63V and VCCW=VCCWH1/2. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VCCWVCCWLK, SR.3 and SR.5 will be set to "1". Successful block erase requires for boot blocks that WP# is VIH and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must be cleared the corresponding block lock-bit. If block erase is attempted when the excepting above conditions, SR.1 and SR.5 will be set to "1". status register mode until a new command is issued. If error is detected on a block during full chip erase operation, WSM stops erasing. Full chip erase operation start from lower address block, finish the higher address block. Full chip erase can not be suspended. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable full chip erasure can only occur when VCC=2.97V-3.63V and VCCW=VCCWH1/2. In the absence of this high voltage, block contents are protected against erasure. If full chip erase is attempted while VCCWVCCWLK, SR.3 and SR.5 will be set to "1". Successful full chip erase requires for boot blocks that WP# is VIH and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must be cleared the corresponding block lock-bit. If all blocks are locked, SR.1 and SR.5 will be set to "1". 4.7 Word/Byte Write Command Word/Byte write is executed by a two-cycle command sequence. Word/Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect the completion of the word/byte write event by analyzing the RY/BY# pin or status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when VCC=2.97V-3.63V and VCCW=VCCWH1/2. In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while VCCWVCCWLK, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte write requires for boot blocks that WP# is VIH and the corresponding block lock-bit be cleared. In parameter and main blocks case, it must be cleared the corresponding block lock-bit. If word/byte write is attempted when the excepting above conditions, SR.1 and SR.4 will be set to "1". 4.6 Full Chip Erase Command This command followed by a confirm command erases all of the unlocked blocks. A full chip erase setup (30H) is first written, followed by a full chip erase confirm (D0H). After a confirm command is written, device erases the all unlocked blocks block by block. This command sequence requires appropriate sequencing. Block preconditioning, erase and verify are handled internally by the WSM (invisible to the system). After the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect full chip erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the full chip erase is complete, status register bit SR.5 should be checked. If erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read Rev. 1.27 LHF80J47 14 4.8 Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to High Z. Specification tWHRZ2 defines the block erase suspend latency. When Block Erase Suspend command write to the CUI, if block erase was finished, the device places read array mode. Therefore, after Block Erase Suspend command write to the CUI, Read Status Register command (70H) has to write to CUI, then status register bit SR.6 should be checked for places the device in suspend mode. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word/Byte Write Suspend command (see Section 4.9), a word/byte write operation can also be suspended. During a word/byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9). VCCW must remain at VCCWH1/2 (the same VCCW level used for block erase) while block erase is suspended. RP# must also remain at VIH. WP# must also remain at VIL or VIH (the same WP# level used for block erase). Block erase cannot resume until word/byte write operations initiated during block erase suspend have completed. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than tERES and both commands are written repeatedly, a longer time is required than standard block erase until the completion of the operation. 4.9 Word/Byte Write Suspend Command The Word/Byte Write Suspend command allows word/byte write interruption to read data in other flash memory locations. Once the word/byte write process starts, writing the Word/Byte Write Suspend command requests that the WSM suspend the Word/Byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word/byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to High Z. Specification tWHRZ1 defines the word/byte write suspend latency. When Word/Byte Write Suspend command write to the CUI, if word/byte write was finished, the device places read array mode. Therefore, after Word/Byte Write Suspend command write to the CUI, Read Status Register command (70H) has to write to CUI, then status register bit SR.2 should be checked for places the device in suspend mode. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word/byte write is suspended are Read Status Register and Word/Byte Write Resume. After Word/Byte Write Resume command is written to the flash memory, the WSM will continue the word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Word/Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 10). VCCW must remain at VCCWH1/2 (the same VCCW level used for word/byte write) while in word/byte write suspend mode. RP# must also remain at VIH. WP# must also remain at VIL or VIH (the same WP# level used for word/byte write). If the time between writing the Word/Byte Write Resume command and writing the Word/Byte Write Suspend command is short and both commands are written repeatedly, a longer time is required than standard word/byte write until the completion of the operation. Rev. 1.27 LHF80J47 15 4.10 Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations while the permanent lock-bit gates block-lock bit modification. With the permanent lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Permanent Lock-Bit command, sets the permanent lock-bit. After the permanent lock-bit is set, block lock-bits and locked block contents cannot altered. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. The set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when VCC=2.97V-3.63V and VCCW=VCCWH1/2. In the absence of this high voltage, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the permanent lock-bit be cleared. If it is attempted with the permanent lock-bit set, SR.1 and SR.4 will be set to "1" and the operation will fail. 4.11 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the permanent lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the permanent lock-bit is set, block lock-bits cannot cleared. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Figure 12). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# Pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when VCC=2.97V-3.63V and VCCW=VCCWH1/2. If a clear block lock-bits operation is attempted while VCCWVCCWLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires that the permanent lock-bit is not set. If it is attempted with the permanent lock-bit set, SR.1 and SR.5 will be set to "1" and the operation will fail. If a clear block lock-bits operation is aborted due to VCCW or VCC transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set, it cannot be cleared. Rev. 1.27 LHF80J47 16 4.12 OTP Program Command OTP program is executed by a two-cycle command sequence. OTP program command(C0H) is written, followed by a second write cycle that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the OTP program and program verify algorithms internally. After the OTP program command sequence is completed, the device automatically outputs status register data when read (see Figure 13). The CPU can detect the completion of the OTP program by analyzing the output data of the RY/BY# pin or status register bit SR.7. When OTP program is completed, status register bit SR.4 should be checked. If OTP program error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in read status register mode until it receives other commands. Reliable OTP program can be executed only when VCC=2.97V-3.63V and VCCW=VCCWH1/2. In the absence of this voltage, memory contents are protected against OTP programs. If OTP program is attempted while VCCWVCCWLK, status register bits SR.3 and SR.4 is set to "1". If OTP write is attempted when the OTP Lock-bit is set, SR.1 and SR.4 is set to "1". 4.13 Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. The lockable two boot blocks are locked when WP#=VIL; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable. If WP# is VIH and block lockbit is not set, boot block can be programmed or erased normally (Unless VCCW is below VCCWLK). WP# is valid only two boot blocks, other blocks are not affected. Rev. 1.27 LHF80J47 Table 5. Write Protection Alternatives(1) Permanent Block WP# Effect Lock-Bit Lock-bit X X X All Blocks Locked. X X X All Blocks Locked. X 0 VIL 2 Boot Blocks Locked. VIH Block Erase and Word/Byte Write Enabled. 1 VIL Block Erase and Word/Byte Write Disabled. VIH Block Erase and Word/Byte Write Disabled. X X X All Blocks Locked. X X X All Blocks Locked. X X VIL All Unlocked Blocks are Erased. 2 Boot Blocks and Locked Blocks are NOT Erased. VIH All Unlocked Blocks are Erased, Locked Blocks are NOT Erased. X X X Set Block Lock-Bit Disabled. X X X Set Block Lock-Bit Disabled. 0 X X Set Block Lock-Bit Enabled. 1 X X Set Block Lock-Bit Disabled. X X X Clear Block Lock-Bits Disabled. X X X Clear Block Lock-Bits Disabled. 0 X X Clear Block Lock-Bits Enabled. 1 X X Clear Block Lock-Bits Disabled. X X X Set Permanent Lock-Bit Disabled. X X X Set Permanent Lock-Bit Disabled. X X X Set Permanent Lock-Bit Enabled. 17 Operation VCCW RP# X VIL VIH Block Erase VCCWLK or >VCCWLK Word/Byte Write Full Chip Erase VCCWLK >VCCWLK X VIL VIH Set Block Lock-Bit VCCWLK >VCCWLK X VIL VIH X VIL VIH Clear Block VCCWLK Lock-Bits >VCCWLK Set X VCCWLK Permanent >VCCWLK VIL Lock-Bit VIH NOTE: 1. X can be VIL or VIH for RP# and WP#, and "0" or "1" for permanent lock-bit and block lock-bit. See DC Characteristics for VCCWLK voltage. Rev. 1.27 LHF80J47 Table 6. Status Register Definition WBWSLBS VCCWS WBWSS 4 3 2 NOTES: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS (ECBLBS) 1 = Error in Block Erase, Full Chip Erase or Clear Block Lock-Bits 0 = Successful Block Erase, Full Chip Erase or Clear Block Lock-Bits SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT STATUS (WBWSLBS) 1 = Error in Word/Byte Write or Set Block/Permanent Lock-Bit 0 = Successful Word/Byte Write or Set Block/Permanent Lock-Bit SR.3 = VCCW STATUS (VCCWS) 1 = VCCW Low Detect, Operation Abort 0 = VCCW OK SR.2 = WORD/BYTE WRITE SUSPEND STATUS (WBWSS) 1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Block Lock-Bit, Permanent Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) 18 WSMS 7 BESS 6 ECBLBS 5 DPS 1 R 0 Check RY/BY# or SR.7 to determine block erase, full chip erase, word/byte write or lock-bit configuration completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase, full chip erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of VCCW level. The WSM interrogates and indicates the VCCW level only after Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when VCCWVCCWH1/2. SR.1 does not provide a continuous indication of permanent and block lock-bit and WP# values. The WSM interrogates the permanent lock-bit, block lock-bit and WP# only after Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/or WP# is VIL. Reading the block lock and permanent lock configuration codes after writing the Read Identifier Codes command indicates permanent and block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. Rev. 1.27 LHF80J47 19 Start Bus Operation Command Comments Write 70H Write Read Status Register Data=70H Addr=X Read Status Register Read Status Register Data Check SR.7 Standby SR.7= 1 0 1=WSM Ready 0=WSM Busy Data=20H Addr=X Data=D0H Addr=Within Block to be Erased Write Erase Setup Write 20H Write Erase Confirm Write D0H, Block Address Read Status Register Data Read Status Register No 0 Suspend Block Erase Suspend Block Erase Loop Standby Check SR.7 1=WSM Ready 0=WSM Busy Repeat for subsequent block erasures. Yes Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode. SR.7= 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Comments SR.3= 0 1 Standby VCCW Range Error Standby Check SR.3 1=VCCW Error Detect Check SR.1 1=Device Protect Detect Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Block Erase Error SR.1= 0 1 Device Protect Error Standby Standby SR.4,5= 0 1 Command Sequence Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. SR.5= 0 1 Block Erase Error Block Erase Successful Figure 6. Automated Block Erase Flowchart Rev. 1.27 LHF80J47 20 Start Bus Operation Command Comments Write 70H Write Read Status Register Data=70H Addr=X Read Status Register Read Status Register Data Check SR.7 SR.7= 1 0 Standby 1=WSM Ready 0=WSM Busy Full Chip Erase Setup Full Chip Erase Confirm Data=30H Addr=X Data=D0H Addr=X Write Write 30H Write Write D0H Read Status Register Data Read Status Register Check SR.7 Standby 1=WSM Ready 0=WSM Busy Full status check can be done after each full chip erase. Write FFH after the last operation to place device in read array mode. SR.7= 1 Full Status Check if Desired 0 Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Comments SR.3= 0 1 Standby VCCW Range Error Check SR.3 1=VCCW Error Detect Check SR.1 Standby 1=Device Protect Detect (All Blocks are locked) SR.1= 0 1 Device Protect Error Standby Check SR.4,5 Both 1=Command Sequence Error Check SR.5 1=Full Chip Erase Error Standby SR.4,5= 0 1 Command Sequence Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. SR.5= 0 Full Chip Erase Successful 1 Full Chip Erase Error Figure 7. Automated Full Chip Erase Flowchart Rev. 1.27 LHF80J47 21 Start Bus Operation Command Comments Write 70H Write Read Status Register Data=70H Addr=X Read Status Register Read Status Register Data Check SR.7 Standby SR.7= 1 0 1=WSM Ready 0=WSM Busy Data=40H or 10H Addr=X Data=Data to Be Written Addr=Location to Be Written Write Setup Word/Byte Write Write 40H or 10H Write Word/Byte Write Write Word/Byte Data and Address Read Status Register Data Read Status Register No 0 Suspend Word/Byte Write Suspend Word/Byte Write Loop Standby Check SR.7 1=WSM Ready 0=WSM Busy Repeat for subsequent word/byte writes. Yes SR full status check can be done after each word/byte write, or after a sequence of word/byte writes. Write FFH after the last word/byte write operation to place device in read array mode. SR.7= 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Comments SR.3= 1 Standby VCCW Range Error Standby Check SR.3 1=VCCW Error Detect Check SR.1 1=Device Protect Detect Check SR.4 1=Data Write Error 0 SR.1= 1 Device Protect Error Standby 0 SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 1 SR.4= Word/Byte Write Error 0 Word/Byte Write Successful Figure 8. Automated Word/Byte Write Flowchart Rev. 1.27 LHF80J47 22 Start Bus Operation Command Comments Write B0H Write Erase Suspend Data=B0H Addr=X Status Register Data Addr=X Check SR.7 Read Read Status Register Standby 1=WSM Ready 0=WSM Busy SR.7= 0 Standby Check SR.6 1=Block Erase Suspended 0=Block Erase Completed Erase Resume Data=D0H Addr=X 1 Write SR.6= 0 Block Erase Completed 1 Read Read or Word/Byte Write ? Word/Byte Write Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Figure 9. Block Erase Suspend/Resume Flowchart Rev. 1.27 LHF80J47 23 Start Bus Operation Command Comments Write B0H Write Word/Byte Write Suspend Data=B0H Addr=X Status Register Data Read Read Status Register Standby Addr=X Check SR.7 1=WSM Ready 0=WSM Busy SR.7= 0 Standby Check SR.2 1=Word/Byte Write Suspended 0=Word/Byte Write Completed Data=FFH Addr=X Read Array locations other Read 1 Write SR.2= 0 Word/Byte Write Completed Read Array 1 Write Word/Byte Write Resume than that being written. Data=D0H Addr=X Write FFH Read Array Data Done Reading Yes No Write D0H Write FFH Word/Byte Write Resumed Read Array Data Figure 10. Word/Byte Write Suspend/Resume Flowchart Rev. 1.27 LHF80J47 24 Start Bus Operation Command Comments Write 70H Write Read Status Register Data=70H Addr=X Read Status Register Read Status Register Data Check SR.7 Standby SR.7= 1 0 Set Block/Permanent Lock-Bit Setup 1=WSM Ready 0=WSM Busy Write Data=60H Addr=X Write 60H Data=01H(Block), Write Write 01H/F1H, Block/Device Address Set Block or Permanent Lock-Bit Confirm F1H(Permanent) Addr=Block Address(Block), Device Address(Permanent) Read Status Register Read Status Register Data Check SR.7 SR.7= 1 Full Status Check if Desired 0 Standby 1=WSM Ready 0=WSM Busy Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode. Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Comments SR.3= 0 1 Standby VCCW Range Error Check SR.3 1=VCCW Error Detect Check SR.1 Standby 1 1=Device Protect Detect Permanent Lock-Bit is Set (Set Block Lock-Bit Operation) SR.1= 0 Device Protect Error Standby Check SR.4,5 Both 1=Command Sequence Error SR.4,5= 0 1 Command Sequence Error Standby Check SR.4 1=Set Lock-Bit Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Set Lock-Bit Error SR.4= 0 1 Set Lock-Bit Successful Figure 11. Set Block and Permanent Lock-Bit Flowchart Rev. 1.27 LHF80J47 25 Start Bus Operation Command Comments Write 70H Write Read Status Register Data=70H Addr=X Read Status Register Read Status Register Data Check SR.7 Standby SR.7= 1 0 Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm 1=WSM Ready 0=WSM Busy Data=60H Addr=X Data=D0H Addr=X Write Write 60H Write Write D0H Read Status Register Data Read Status Register Check SR.7 Standby 1=WSM Ready 0=WSM Busy 0 Write FFH after the Clear Block Lock-Bits operation to place device in read array mode. SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Comments 1 SR.3= 0 Standby VCCW Range Error Check SR.3 1=VCCW Error Detect Check SR.1 Standby 1=Device Protect Detect Permanent Lock-Bit is Set SR.1= 0 1 Device Protect Error Standby Check SR.4,5 Both 1=Command Sequence Error SR.4,5= 0 1 Standby Command Sequence Error Check SR.5 1=Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the Status Register before attempting retry or other error recovery. 1 SR.5= 0 Clear Block Lock-Bits Successful Clear Block Lock-Bits Error Figure 12. Clear Block Lock-Bits Flowchart Rev. 1.27 LHF80J47 26 Start Bus Operation Command Comments Write 70H Write Read Status Register Data=70H Addr=X Read Status Register Read Status Register Data Check SR.7 Standby SR.7= 1 0 1=WSM Ready 0=WSM Busy Data=C0H Addr=X Data=Data to Be Written Addr=Location to Be Written Write Setup OTP Program Write C0H Write OTP Program Write Data and Address Read Status Register Data Read Status Register Standby Check SR.7 1=WSM Ready 0=WSM Busy 0 Repeat for subsequent OTP programs. SR full status check can be done after each OTP program, or after a sequence of OTP programs. Write FFH after the last OTP program operation to place device in read array mode. SR.7= 1 Full Status Check if Desired OTP Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Bus Operation Command Comments SR.3= 0 1 Standby VCCW Range Error Standby Check SR.3 1=VCCW Error Detect Check SR.1 1=Device Protect Detect Check SR.4 1=Data Write Error SR.1= 0 1 Device Protect Error Standby SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 1 SR.4= 0 OTP Program Error OTP Program Successful Figure 13. Automated OTP Program Flowchart Rev. 1.27 LHF80J47 27 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1F ceramic capacitor connected between its VCC and GND and between its VCCW and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 VCCW Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VCCW Power supply trace. The VCCW pin supplies the memory cell current for word/byte writing and block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VCCW supply traces and decoupling will decrease VCCW voltage spikes and overshoots. 5.2 RY/BY# and WSM Polling RY/BY# is an open drain output that should be connected to VCC by a pull up resistor to provides a hardware method of detecting block erase, full chip erase, word/byte write and lock-bit configuration completion. It transitions low after block erase, full chip erase, word/byte write or lockbit configuration commands and returns to VOH (while RY/BY# is pull up) when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also High Z when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend or reset modes. 5.5 VCC, VCCW, RP# Transitions Block erase, full chip erase, word/byte write and lock-bit configuration are not guaranteed if VCCW falls outside of a valid VCCWH1/2 range, VCC falls outside of a valid 2.97V3.63V range, or RP#VIH. If VCCW error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, full chip erase, word/byte write or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter reset mode. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VCCW or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from reset mode or after VCC transitions below VLKO. Rev. 1.27 LHF80J47 28 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erase, full chip erase, word/byte write or lock-bit configuration during power transitions. Upon power-up, the device is indifferent as to which power supply (VCCW or VCC) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VCCW is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI's twostep command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP#=VIL regardless of its control inputs state. 5.8 Data Protection Method Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block When a lock bit is set, the corresponding block (includes the 2 boot blocks) is protected against overwriting. By setting a WP# to low, only the 2 boot blocks can be protected against overwriting. By using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). The permanent lock bit can be used to prevent false block bit setting. For further information on setting/resetting lock-bit, refer to the specification. (See chapter 4.10 and 4.11.) 2) Data protection through VCCW When the level of VCCW is lower than VCCWLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage, refer to the specification. (See chapter 6.2.3.) 3) Data protection through RP# When the RP# is kept low during read mode, the flash memory will be reset mode, then write protecting all blocks. When the RP# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. For the details of RP# control, refer to the specification. (See chapter 5.6 and 6.2.7.) 5.7 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. Rev. 1.27 LHF80J47 29 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration ................0C to +70C(1) Storage Temperature During under Bias ............................... -10C to +80C During non Bias ................................ -65C to +125C Voltage On Any Pin (except VCC and VCCW) ........... -0.5V to VCC+0.5V(2) VCC Supply Voltage................................ -0.2V to +4.6V(2) VCCW Supply Voltage......................... -0.2V to +13.0V(2,3) Output Short Circuit Current................................100mA(4) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC and VCCW pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins are VCC+0.5V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 3. Maximum DC voltage on VCCW may overshoot to +13.0V for periods <20ns. Applying 12V0.3V to VCCW during erase/write can only be done for a maximum of 1000 cycles on each block. VCCW may be connected to 12V0.3V for a total of 80 hours maximum. 4. Output shorted for no more than one second. No more than one output shorted at a time. 6.2 Operating Conditions Temperature and VCC Operating Conditions Symbol Parameter Min. Max. Unit TA Operating Temperature 0 +70 C VCC VCC Supply Voltage (2.97V-3.63V) 2.97 3.63 V Test Condition Ambient Temperature 6.2.1 Capacitance(1) Symbol Parameter Input Capacitance Output Capacitance TA=+25C, f=1MHz Typ. Max. 7 10 9 12 Unit pF pF Condition VIN=0.0V VOUT=0.0V CIN COUT NOTE: 1. Sampled, not 100% tested. Rev. 1.27 LHF80J47 6.2.2 AC Input/Output Test Conditions 30 3.0 INPUT 0.0 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. 1.5 TEST POINTS 1.5 OUTPUT Figure 14. Transient Input/Output Reference Waveform for VCC=2.97V-3.63V Test Configuration Capacitance Loading Value Test Configuration CL(pF) VCC=2.97V-3.63V 50 1N914 1.3V RL=3.3k DEVICE UNDER TEST CL Includes Jig Capacitance CL OUT Figure 15. Transient Equivalent Testing Load Circuit Rev. 1.27 LHF80J47 6.2.3 DC Characteristics DC Characteristics VCC=2.97V-3.63V Notes Typ. Max. 1 0.5 1 1,3,6 2 15 A 0.5 31 Sym. ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Unit A A 0.2 ICCAS ICCD ICCR VCC Auto Power-Save Current VCC Reset Power-Down Current VCC Read Current 1,5,6 2 1 1,6 15 2 2 mA 15 15 25 A A mA 30 ICCW ICCE ICCWS ICCES ICCWS ICCWR ICCWAS ICCWD ICCWW ICCWE ICCWWS ICCWES VCC Word/Byte Write or Set LockBit Current VCC Block Erase, Full Chip Erase or Clear Block Lock-Bits Current VCC Word/Byte Write or Block Erase Suspend Current VCCW Standby or Read Current VCCW Auto Power-Save Current VCCW Reset Power-Down Current VCCW Word/Byte Write or Set LockBit Current VCCW Block Erase, Full Chip Erase or Clear Block Lock-Bits Current VCCW Word/Byte Write or Block Erase Suspend Current 1,7 1,7 1,2 1 1,5,6 0.1 1 1,7 1,7 1 0.1 12 8 10 5 5 40 30 25 20 200 5 5 4 4 1 2 10 17 12 17 12 6 15 200 mA mA mA mA mA mA A A A A mA mA mA mA A Test Conditions VCC=VCCMax. VIN=VCC or GND VCC=VCCMax. VOUT=VCC or GND CMOS Level Inputs VCC=VCCMax. CE#=RP#=VCC0.2V TTL Level Inputs VCC=VCCMax. CE#=RP#=VIH CMOS Level Inputs VCC=VCCMax. CE#=GND0.2V RP#=GND0.2V IOUT(RY/BY#)=0mA CMOS Level Inputs VCC=VCCMax., CE#=GND f=5MHz, IOUT=0mA TTL Level Inputs VCC=VCCMax., CE#=GND f=5MHz, IOUT=0mA VCCW=2.97V-3.63V VCCW=11.7V-12.3V VCCW=2.97V-3.63V VCCW=11.7V-12.3V CE#=VIH VCCWVCC VCCW>VCC CMOS Level Inputs VCC=VCCMax. CE#=GND0.2V RP#=GND0.2V VCCW=2.97V-3.63V VCCW=11.7V-12.3V VCCW=2.97V-3.63V VCCW=11.7V-12.3V VCCW=VCCWH1/2 Rev. 1.27 LHF80J47 DC Characteristics (Continued) VCC=2.97V-3.63V Notes Min. Max. 7 -0.5 0.8 7 VCC 2.0 +0.5 3,7 0.4 7 7 2.4 0.85 VCC VCC -0.4 32 Sym. VIL VIH VOL VOH1 VOH2 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) Unit V V V V V V Test Conditions VCC=VCC Min. IOL=2.0mA VCC=VCC Min. IOH=-2.0mA VCC=VCC Min. IOH=-2.5mA VCC=VCC Min. IOH=-100A VCCWLK VCCW Lockout during Normal 4,7 1.0 V Operations VCCWH1 VCCW during Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit 2.97 3.63 V Configuration Operations VCCWH2 VCCW during Block Erase, Full Chip 8 Erase, Word/Byte Write or Lock-Bit 11.7 12.3 V Configuration Operations VLKO VCC Lockout Voltage 2.0 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25C. 2. ICCWS and ICCES are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 3. Includes RY/BY#. 4. Block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when VCCWVCCWLK, and not guaranteed in the range between VCCWLK(max.) and VCCWH1(min.), between VCCWH1(max.) and VCCWH2(min.) and above VCCWH2(max.). 5. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more than 300ns while read mode. 6. About all of pin except describe Test Conditions, CMOS level inputs are either VCC0.2V or GND0.2V, TTL level inputs are either VIL or VIH. 7. Sampled, not 100% tested. 8. Applying 12V0.3V to VCCW during erase/write can only be done for a maximum of 1000 cycles on each block. VCCW may be connected to 12V0.3V for a total of 80 hours maximum. Rev. 1.27 LHF80J47 6.2.4 AC Characteristics - Read-Only Operations(1) Sym. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH VCC=2.97V-3.63V, TA=0C to +70C Parameter Notes Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output in Low Z CE# High to Output in High Z OE# to Output in Low Z OE# High to Output in High Z Output Hold from Address, CE# or OE# Change, Whichever Occurs First BYTE# to Output Delay BYTE# Low to Output in High Z CE# to BYTE# High or Low Min. 70 Max. 70 70 600 50 0 55 0 20 0 70 30 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 33 2 2 3 3 3 3 3 tFVQV 3 tFLQZ 3 tELFV 3,4 NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. If BYTE# transfer during reading cycle, exist the regulations separately. Rev. 1.27 LHF80J47 34 VIH ADDRESSES(A) Standby Device Address Selection Address Stable tAVAV Data Valid VIL VIH CE#(E) VIL VIH OE#(G) tEHQZ VIL VIH WE#(W) tGHQZ tGLQV tELQV tGLQX tELQX tOH HIGH Z VIL VOH DATA(D/Q) (DQ0-DQ15) HIGH Z tAVQV Valid Output VOL VCC tPHQV VIH RP#(P) VIL Figure 16. AC Waveform for Read Operations Rev. 1.27 LHF80J47 35 Standby VIH ADDRESSES(A) Device Address Selection Address Stable tAVAV Data Valid VIL VIH CE#(E) tELQV tEHQZ tAVQV tGLQV tGHQZ tFVQV VIL VIH OE#(G) VIL VIH BYTE#(F) VIL tELFV VOH DATA(D/Q) (DQ0-DQ7) tGLQX Data Output tELQX tFLQZ Valid Output tOH HIGH Z HIGH Z VOL VOH DATA(D/Q) (DQ8-DQ15) HIGH Z Data Output HIGH Z VOL Figure 17. BYTE# timing Waveform Rev. 1.27 LHF80J47 6.2.5 AC Characteristics - Write Operations(1) Sym. VCC=2.97V-3.63V, TA=0C to +70C Parameter Notes Min. 70 1 10 50 100 100 50 50 0 0 10 30 Max. Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 36 tAVAV Write Cycle Time tPHWL RP# High Recovery to WE# Going Low 2 tELWL CE# Setup to WE# Going Low tWLWH WE# Pulse Width tSHWH WP#VIH Setup to WE# Going High 2 tVPWH VCCW Setup to WE# Going High 2 tAVWH Address Setup to WE# Going High 3 tDVWH Data Setup to WE# Going High 3 tWHDX Data Hold from WE# High tWHAX Address Hold from WE# High tWHEH CE# Hold from WE# High tWHWL WE# Pulse Width High tWHRL WE# High to RY/BY# Going Low or SR.7 Going "0" 100 tWHGL Write Recovery before Read 0 tQVVL VCCW Hold from Valid SRD, RY/BY# High Z 2,4 0 tQVSL WP# VIH Hold from Valid SRD, RY/BY# High Z 2,4 0 tFVWH BYTE# Setup to WE# Going High 5 50 tWHFV BYTE# Hold from WE# High 5 70 NOTES: 1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration. 4. VCCW should be held at VCCWH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration success (SR.1/3/4/5=0). 5. If BYTE# switch during reading cycle, exist the regulations separately. Rev. 1.27 LHF80J47 37 } tWHAX tWHGL tWHQV1,2,3,4 tWHFV tWHRL VIH ADDRESSES(A) AIN AIN tAVWH VIL VIH CE#(E) tAVAV VIL VIH OE#(G) tELWL tWHEH VIL tWHWL VIH WE#(W) VIL VIH DATA(D/Q) High Z tPHWL tWLWH tDVWH tWHDX DIN tFVWH DIN Valid SRD DIN VIL VIH BYTE#(F) VIL RY/BY#(R) (SR.7) High Z ("1") VOL ("0") VIH tSHWH WP#(S) VIL VIH RP#(P) VIL tVPWH VCCWH1/2 VCCW(V) VCCWLK VIL NOTES: 1. VCC power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Figure 18. AC Waveform for WE#-Controlled Write Operations } } tQVSL tQVVL } } } 1 2 3 4 5 6 Rev. 1.27 LHF80J47 6.2.6 Alternative CE#-Controlled Writes(1) Sym. VCC=2.97V-3.63V, TA=0C to +70C Parameter Notes Min. 70 1 0 50 100 100 50 50 0 0 0 30 Max. Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 38 tAVAV Write Cycle Time tPHEL RP# High Recovery to CE# Going Low 2 tWLEL WE# Setup to CE# Going Low tELEH CE# Pulse Width tSHEH WP#VIH Setup to CE# Going High 2 tVPEH VCCW Setup to CE# Going High 2 tAVEH Address Setup to CE# Going High 3 tDVEH Data Setup to CE# Going High 3 tEHDX Data Hold from CE# High tEHAX Address Hold from CE# High tEHWH WE# Hold from CE# High tEHEL CE# Pulse Width High tEHRL CE# High to RY/BY# Going Low or SR.7 Going "0" 100 tEHGL Write Recovery before Read 0 tQVVL VCCW Hold from Valid SRD, RY/BY# High Z 2,4 0 tQVSL WP# VIH Hold from Valid SRD, RY/BY# High Z 2,4 0 tFVEH BYTE# Setup to CE# Going High 5 50 tEHFV BYTE# Hold from CE# High 5 70 NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN and DIN for block erase, full chip erase, word/byte write or lock-bit configuration. 4. VCCW should be held at VCCWH1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration success (SR.1/3/4/5=0). 5. If BYTE# switch during reading cycle, exist the regulations separately. Rev. 1.27 LHF80J47 39 } } tEHAX tEHGL tEHQV1,2,3,4 tEHFV tEHRL VIH ADDRESSES(A) AIN AIN tAVEH tEHEL tELEH tDVEH VIL VIH CE#(E) tAVAV VIL VIH OE#(G) VIL VIH WE#(W) VIL VIH DATA(D/Q) tWLEL High Z tPHEL DIN tEHWH tEHDX DIN tFVEH VIL VIH BYTE#(F) VIL RY/BY#(R) (SR.7) High Z ("1") VOL ("0") VIH tSHEH WP#(S) VIL VIH RP#(P) VIL tVPEH VCCWH1/2 VCCW(V) VCCWLK VIL NOTES: 1. VCC power-up and standby. 2. Write each setup command. 3. Write each confirm command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Figure 19. AC Waveform for CE#-Controlled Write Operations } } Valid SRD DIN tQVSL tQVVL } } 1 2 3 4 5 6 Rev. 1.27 LHF80J47 6.2.7 Reset Operations 40 High Z RY/BY#(R) ("1") (SR.7) VOL ("0") VIH RP#(P) VIL tPLPH (A)Reset During Read Array Mode High Z RY/BY#(R) ("1") (SR.7) VOL ("0") RP#(P) VIH VIL tPLPH (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration 2.97V VCC VIL VIH RP#(P) VIL (C)RP# rising Timing t2VPH tPLRZ Figure 20. AC Waveform for Reset Operation Reset AC Specifications Sym. tPLPH tPLRZ Parameter RP# Pulse Low Time RP# Low to Reset during Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration VCC 2.97V to RP# High Notes 2 1,2 Min. 100 Max. 30 Unit ns s t2VPH 2,3 100 ns NOTES: 1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing, the reset will complete within 100ns. 2. A reset time, tPHQV, is required from the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also has been in stable there. Rev. 1.27 LHF80J47 6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance(3) VCC=2.97V-3.63V, TA=0C to +70C VCCW=2.97V-3.63V Parameter Notes Min. Typ.(1) Max. Word Write Time 32K word Block 2 33 200 4K word Block 2 36 200 Byte Write Time 64K byte Block 2 31 200 8K byte Block 2 32 200 Block Write Time 32K word Block 2 1.1 4 (In word mode) 4K word Block 2 0.15 0.5 Block Write Time 64K byte Block 2 2.2 7 (In byte mode) 8K byte Block 2 0.3 1 32K word Block Block Erase Time 2 1.2 6 64K byte Block 4K word Block 2 0.6 5 8K byte Block Full Chip Erase Time 2 22.8 114 Set Lock-Bit Time Clear Block Lock-Bits Time Word/Byte Write Suspend Latency Time to Read Block Erase Suspend Latency Time to Read Latency Time from Block Erase Resume Command to Block Erase Suspend Command 2 2 4 4 5 600 56 1 6 16 200 5 15 30 600 VCCW=11.7V-12.3V Min. Typ.(1) Max. 20 27 19 26 0.66 0.12 1.4 0.25 0.9 0.5 17.5 42 0.69 6 16 15 30 41 Sym. tWHQV1 tEHQV1 Unit s s s s s s s s s s s s s s s s tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHRZ1 tEHRZ1 tWHRZ2 tEHRZ2 tERES NOTES: 1. Typical values measured at TA=+25C and VCC=3.0V, VCCW=3.0V or 12.0V. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. 4. A latency time is required from issuing suspend command(WE# or CE# going high) until RY/BY# going High Z or SR.7 going "1". 5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than tERES and both commands are written repeatedly, a longer time is required than standard block erase until the completion of the operation. Rev. 1.27 i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) VCC GND VIH RP# (P) (RST#) VCCW *2 (V) (VPP) ADDRESS (A) VIL tF VIH CE# (E) tVR t2VPH *1 tR tPHQV VIL VCCWH1/2 (VPPH1/2) GND tR or tF VIH tAVQV Valid Address tELQV tR tR or tF VIL VIH WE# (W) VIL tF VIH OE# (G) tGLQV tR VIL VIH WP# (S) VIL VOH DATA (D/Q) VOL High Z Valid Output *1 t5VPH for the device in 5V operations. *2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP) to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations. See the application note AP-007-SW-E for details. Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Rev. 1.10 ii A-1.1.1 Rise and Fall Time Symbol tVR tR tF VCC Rise Time Parameter Notes 1 1, 2 1, 2 Min. 0.5 Max. 30000 1 1 Unit s/V s/V s/V Input Signal Rise Time Input Signal Fall Time NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. tR(Max.) and tF(Max.) for RP# (RST#) are 20s/V. Rev. 1.10 iii A-1.2 Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal VIH (Min.) Input Signal VIH (Min.) VIL (Max.) VIL (Max.) Input Signal Input Signal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure A-2. Waveform for Glitch Noises See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.). Rev. 1.10 iv A-2 RELATED DOCUMENT INFORMATION(1) Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit NOTE: 1. International customers should contact their local SHARP or distribution sales office. Rev. 1.10 |
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